Chip Design Takes Months. Visibl Semiconductors Wants to Cut That to Weeks.

The Macro: The Semiconductor Industry Has a Coordination Problem Nobody Talks About

Everyone knows chips are hard to make. The physics is extreme. The fabrication is measured in nanometers. The capital expenditure is measured in billions. TSMC, Samsung, and Intel collectively spend more on factories than most countries spend on infrastructure.

But here is the part of the semiconductor story that does not get enough attention: the design process is a coordination nightmare that has not fundamentally changed in decades.

A modern chip design involves hundreds of engineers working across multiple teams, using dozens of specialized EDA (electronic design automation) tools, over a timeline that stretches from months to years. The tools are powerful but siloed. Cadence and Synopsys dominate the EDA market with products that are essentially the Photoshop and Illustrator of chip design: incredibly capable, incredibly complex, and not particularly good at talking to each other.

The result is that a huge percentage of chip design time is not spent on actual design work. It is spent on coordination. Managing dependencies between teams. Tracking which blocks are done and which are blocking other blocks. Detecting when a design change in one module has quietly broken an assumption in another module. Running timing closure iterations that should have caught a problem three weeks earlier.

This coordination overhead is expensive in a very direct way. A single tapeout, the point at which a chip design gets sent to the fab for manufacturing, can cost between $5 million and $50 million depending on the process node. If you miss your tapeout window because a design issue was caught too late, you do not just lose time. You lose the entire cost of the fab run, and you push your product launch by months.

The semiconductor industry ran $575 billion in global revenue in 2024 according to the Semiconductor Industry Association. And a meaningful fraction of the cost structure is driven by design inefficiency, not fabrication complexity. This is the problem Visibl Semiconductors is attacking.

The Micro: Two Founders, an Orchestrator, and the Audacity to Tackle EDA

Visibl Semiconductors came out of Y Combinator’s Winter 2026 batch, founded by Bryce Neil (CEO) and Jordon Kashanchi (CTO) out of San Francisco. The company positions itself as “the coordination layer for chip design,” which is a very specific and very ambitious claim.

Their product is called Orchestrator, and the pitch is that it uses AI agents to automate the coordination work that currently eats up engineering time during chip design. The tagline on their site is “accelerate your tapeout with AI-powered EDA tools,” which tells you exactly who they are building for and what outcome they are promising.

The concept of AI agents for chip design is different from AI for chip design in an important way. Companies like Synopsys (with DSO.ai) and Cadence (with Cerebrus) have been adding machine learning to their existing tools to optimize specific steps in the design flow, things like placement and routing, timing optimization, and power analysis. These are point solutions. They make individual steps faster.

Visibl is going after the orchestration layer that sits above those individual tools. Think of it as the difference between making each musician in an orchestra play faster and hiring a better conductor. The individual tools are already quite good. The problem is that nobody is coordinating the overall flow intelligently.

Design drift detection is one of the capabilities they highlight. In a large chip design, it is common for teams working on different blocks to gradually drift out of alignment with each other. Interface assumptions change. Timing budgets get consumed in one block without notification to dependent blocks. By the time someone notices, weeks of work may need to be redone. An AI system that continuously monitors for drift and flags conflicts early could save enormous amounts of rework.

The competitive position is interesting because Visibl is not directly competing with Cadence or Synopsys. They are building a layer that sits on top of the existing EDA toolchain. This is strategically smart. The semiconductor industry is not going to rip out Cadence and Synopsys. Those tools are too deeply embedded in every design flow. But a coordination layer that makes those tools work together more effectively has a much lower adoption barrier.

The Verdict

This is a hard problem being attacked by a small team, and that combination could go either way. The semiconductor industry is notoriously conservative about adopting new tools. Design teams have spent years building flows around their existing EDA toolchains, and introducing a new orchestration layer is not a casual decision.

But the value proposition is clear and quantifiable. If Visibl can demonstrate that their Orchestrator catches design drift that would have caused a tapeout slip, the ROI is immediate and massive. One prevented slip pays for the tool for years.

I want to see two things from Visibl in the next six months. First, a published case study showing measurable tapeout acceleration. Not a demo. Not a simulation. An actual chip design that went faster because Orchestrator caught something the existing flow would have missed. Second, clarity on which process nodes and design methodologies they support. A tool that works great for digital designs at 28nm but not for mixed-signal at 5nm has a very different market than one that handles both.

The semiconductor industry needs better coordination tools. That is not controversial. The question is whether a two-person startup from YC can build enough trust with chip design teams to get in the door. Bryce and Jordon have picked one of the hardest possible markets to sell into and one of the most rewarding if they can pull it off.

The chips have to get designed. The teams have to coordinate. If Visibl makes that coordination meaningfully better, they will not lack for customers.