SigmanticAI Is Building Cursor for Chip Design, and Siemens Is Already Paying Attention

The Macro: Chip Design Verification Is the Bottleneck Nobody Outside Semiconductors Talks About

Here is a number that should bother you: verification consumes roughly 70% of the total effort in semiconductor design. Not the creative work of designing the chip architecture. Not the synthesis or manufacturing. Verification. The process of writing thousands of lines of SystemVerilog testbench code to prove that the chip you designed actually does what you think it does.

This is not a small industry. The global semiconductor market hit $627 billion in 2024 and is projected to reach $1 trillion by 2030. The EDA (electronic design automation) tools market alone is worth $16 billion. Synopsys and Cadence, the two companies that dominate EDA, are each worth over $70 billion. This is real money, and a massive chunk of the engineering time within this market goes to writing verification code that is tedious, error-prone, and brutally time-consuming.

The verification problem is specific. When a chip designer writes RTL (Register Transfer Level) code in Verilog or VHDL, they need to prove that the logic behaves correctly under every possible input condition. This requires building UVM (Universal Verification Methodology) testbenches, writing constrained-random stimulus generators, defining functional coverage models, and creating formal assertions. A single verification engineer might spend months writing testbench infrastructure before a single meaningful test runs.

AI coding tools have ignored this entirely. Cursor, Copilot, Windsurf, Cline. They are all trained on Python, JavaScript, TypeScript, and Go. They are good at web development and general-purpose software engineering. Ask any of them to generate a UVM testbench with proper agent topology, a sequencer, and a scoreboard, and you will get output that is syntactically plausible and functionally useless. The training data is simply not there.

This is what makes the “Cursor for Chip Design” pitch more than marketing. It is pointing at a genuine gap where general-purpose AI coding tools cannot compete because they were never trained on the right data.

The Micro: Fine-Tuned Verilog Models That Actually Pass Synthesis

Rohil Khare and Tamzid Razzaque co-founded SigmanticAI in Dublin, California, and went through Y Combinator Summer 2025. Their YC partner is Diana Hu.

The product automates the hardware verification workflow. You feed it your RTL design specifications, and SigmanticAI generates UVM testbenches, stimulus patterns, functional coverage models, and SVA/PSL assertions. The output integrates with existing simulators, which is critical because no chip design team is going to abandon their Synopsys VCS or Cadence Xcelium setup for a startup’s unproven platform.

The technical approach is what separates this from a wrapper around a general-purpose LLM. SigmanticAI has fine-tuned language models specifically on Verilog and SystemVerilog code, and they use reinforcement learning to refine the generated code until it passes synthesis checks. That last part matters enormously. In chip design, code that looks correct but does not synthesize is worthless. The RL feedback loop that validates output against actual synthesis tools is the kind of domain-specific engineering that a generic AI assistant cannot replicate.

The product lives in a VSCode fork, which keeps the developer experience familiar. Chip designers are not going to learn a new IDE just to try an AI tool. Meeting them where they already work is the right call.

Their benchmarks claim 10% better accuracy than Cursor on one-shot verification tasks using the same underlying LLM. That delta comes entirely from the fine-tuning and the domain-specific training data. They also claim 10x faster generation compared to manual coding, and 100% production-ready UVM-compliant output. The 100% claim is bold and I would want to see it tested on complex real-world designs, but the directional claim is credible given the fine-tuning approach.

Siemens is listed as a partner, and Pear VC is an investor alongside Y Combinator. The Siemens relationship is significant because Siemens EDA (formerly Mentor Graphics) is one of the three major EDA vendors. Having them as a partner rather than a competitor suggests that SigmanticAI is positioning as a complement to existing toolchains, not a replacement.

They offer on-premises deployment, which is non-negotiable in semiconductors. Chip designs are among the most closely guarded intellectual property in the world. No semiconductor company is going to send their RTL to a cloud API. On-prem deployment is not a feature here. It is table stakes.

The Verdict

SigmanticAI is attacking one of the most valuable and least addressed problems in the AI coding tools market. The semiconductor verification bottleneck is real, expensive, and growing as chip designs become more complex. Every new AI accelerator, every new automotive chip, every new mobile SoC needs more verification, and the supply of experienced verification engineers is not keeping up.

The competitive moat is the fine-tuned Verilog models. Any company can wrap a general-purpose LLM and point it at hardware description languages. Very few can build models that produce output which actually passes synthesis and meets UVM compliance standards. That requires domain expertise that takes years to build, and SigmanticAI has a head start.

My concern is market size at the startup level. The total addressable market is huge in dollar terms, but the number of potential customers is relatively small. There are maybe a few thousand semiconductor companies in the world that do serious chip design. Enterprise sales cycles in semiconductors are long. Security reviews are intense. The product has to be genuinely better than what experienced verification engineers can do manually, because these teams are conservative and the cost of a verification miss is a multi-million dollar chip respin.

At 30 days, I want to see the tool running on a non-trivial design, something with a real bus protocol or a multi-clock-domain architecture. At 60 days, the question is whether the generated testbenches find real bugs that the design team missed. At 90 days, I want to know if any tapeout has gone through with SigmanticAI-generated verification in the critical path.

If the output is reliable enough for production use, this company is going to be very valuable. The semiconductor industry spends billions on verification every year, and nobody else is building the right tool for it.